This invention relates to electronic timing circuits and particularly to multiple phase clock signal generators. More specifically, it relates to such generators which provide adjustable spacing between the multiple phase clock signals.
Electronic logic circuits require accurate timing information and in many applications a number of clock signals having interdependent relationships are necessary. As it has been found generally preferable to derive these multiple clock signals, or multiple phase clock signals, from a common source, clock circuits have been designed to operate upon a single clock input (generated by an external or internal oscillator) to produce therefrom the multiple clock signals having the desired phasal relationship.
The prior art is replete with multiple phase clock circuits. For example, in U.S. Pat. No. 3,735,277, issued May 22, 1973, to Mr. F. M. Wanlass, two-bit shift registers are used to provide four distinct and overlapping clock pulses. In many cases, however, it is desirable to have multiple phase clock signals which do not overlap in time. One such circuit, which provides nonoverlapping multiple phase clock signals, is shown in U.S. Pat. No. 3,668,436, issued June 6, 1972, to S. H. Bacon. In that circuit a pair of complementary logic signals is provided by an oscillator. One signal is gated to each of two amplifiers and the output of each amplifier is used to directly control the gating to the other amplifier. The gating is arranged so that an output from one amplifier is prevented by grounding its input whenever the other amplifier is producing an output. Hence, the amplifier which would normally begin to operate (or turn ON) is maintained in an OFF state as long as the gating signal from the other amplifier causes its input to be grounded. This arrangement prevents simultaneous production of clock pulses from both amplifiers and therefore insures that no significant overlap will occur between the multiple phase output signals. However, it does not provide separation between the phases, and a defined spacing between clock phases is, of course, useful in many applications. In addition, an inherent effect of grounding the input is to create a large power dissipation when the amplifier is maintained OFF, and since reduced power consumption is a generally desirable goal, this is an unattractive aspect of the circuit.
Accordingly, it is an objective of the present invention to provide an improved multiple phase clock circuit.
It is a particular object of the invention to provide a multiple phase clock circuit which produces multiple clock phases separated by defined and selectable time intervals.
It is also an object of the invention to provide a multiple phase circuit which avoids unnecessary power dissipation.
It is a further object to provide a multiple phase clock circuit which permits control of the rise and fall characteristics of the multiple clock phases.
It is an additional object to provide a multiple phase clock circuit which provides more than two clock phases.